1. Field of the Invention
This invention relates to the field of microprocessors, and in particular to microprocessors having a partitioned memory space.
2. Description of Related Art
An 8-bit data structure and 16-bit address structure has been, and continues to be, a common architecture for low cost microprocessors, or microcontrollers, such as the 80C51 family of processors, and others, that have a legacy that extends back for decades. During these decades, a number of software/firmware applications and routines have been developed.
To remain competitive, application developers continually add features and functions to devices that use microprocessors. Unfortunately, the 16-bit address structure of common processors limits the size of programs, or the amount of data, that can be embodied within these devices. Larger capacity devices, such as 32-bit processors, can address a larger program or data space, but are typically more expensive than conventional 8-bit processors. Moving an existing application from one processor family to another in order to provide a larger addressable space for adding additional features, however, typically requires a substantial investment. The development personnel must be trained to use the new processor; libraries of xe2x80x9cutility programsxe2x80x9d, such as mathematical routines and interrupt routines, must be rewritten for the new processor; time-dependent routines must be tested and verified on the new processor; idiosyncratic behavior of the new processor must be discovered and overcome; and so on.
Expanding the addressing space of an existing processor alleviates a number of the difficulties associated with a transition to a new processor, but also introduces a number of compatibility issues with applications and routines that were developed for the existing shorter-address processor. Conventionally, as additional memory access features are provided to a processor family, additional commands are provided to support these features. These additional commands are specifically designed to maintain compatibility with xe2x80x9clegacyxe2x80x9d applications that were developed prior to the availability of these new features, or to provide compatibility with existing architectural features of the processor family. For example, the 8051 processor includes access to an internal memory or an external memory. The internal memory is limited to 256 bytes, using an 8-bit addressing scheme with a range of 0 to 255 (28xe2x88x921). The external memory can have addresses that extend through the entire 16-bit addressing scheme, with a range of 0 to 216xe2x88x921 (65, 535). These different memories are referred to as distinct memory spaces. Note that each memory space is accessible through the entire range provided by the number of bits used for addressing, thereby optimizing the use of addressing bits. That is, in the above example, all of the possible address values (0-65,535) that can be encoded by 16 bits can refer to the external memory, and all of the possible address values (0-255) that can be encoded by 8 bits can refer to the internal memory. Other memory partitioning schemes allocate sub-sets of the possible address values to each memory space, which can result in xe2x80x98gapsxe2x80x99 of memory utilization at the predefined boundaries of these sub-sets. Note, however, that by providing each space with the full range of available address bits, each memory space includes address values that are common to the other. That is, because the first 256 addresses are not reserved exclusively for the internal data memory space, the internal and external data memory spaces include addresses in the range of 0 to 255. To distinguish between an access to an internal memory element having an address between 0 and 255 and an external memory element that also has an address between 0 and 255, different program instructions are provided. A set of xe2x80x9cMOVxe2x80x9d instructions provides access to the internal memory space, and a set of xe2x80x9cMOVXxe2x80x9d instructions provides access to the external memory space. Each of the instructions in each set comprises a MOV or MOVX command, as required, typically followed by a reference with which to determine the particular memory location in the corresponding memory space being accessed. The reference value may be, for example, the address of a register that contains an 8-bit address, or, in the case of the external memory space, a register pair that contains a 16-bit address. Commonly used instructions include both the command and the reference to the register or register pair in a single 8-bit byte, to conserve the memory space required for storing the instruction.
In like manner, the program code is stored in a distinct memory space, the xe2x80x9cprogram memoryxe2x80x9d. In order to provide a full range of addresses within the available bits used for addressing the program code, typically 16 bits, the program memory also has an address range of 0 to 65,535 (216xe2x88x921). To distinguish an access to program code from access to internal or external data items, another distinct instruction, xe2x80x9cMOVCxe2x80x9d is provided. This instruction includes a xe2x80x9cMOVCxe2x80x9d command followed by a reference from which to determine the particular memory location in the program memory space that is being accessed. Note that these distinct MOV, MOVX, MOVC instructions, and potentially others, are required because each of the memory spaces have at least one address that is common to an address of another memory space. Note also that the distinct memory spaces are provided to minimize the size of the memory required to store the program instructions that access these memory spaces.
Conventionally, following this same scheme, a new architecture that allows access to a larger memory space, via a three-byte addressing scheme for example, can be supported by expanding the definition of existing program instructions (MOV, MOVX, MOVC, etc.) to include a three-byte (24-bit) address range (0 to (224xe2x88x921)), as discussed further below with regard to FIG. 2. To maintain compatibility with legacy programs, this expansion would be consistent with the existing use of distinct memory spaces. In this manner, programs and subroutines can continue to use the optimized addressing schemes developed for multiple memory spaces as needed.
Although the use of discrete memory spaces facilitates a minimization of the number of bits required for addressing, it requires an explicit determination of which memory space is being accessed at any given time. At the assembly-language level of programming, this task is not excessively burdensome, because the assembly-language programmer is typically aware of the allocation of data memory between internal and external resources, and is aware of whether the referenced item is a program item or a data item. This awareness, however, is contrary to the general principles of programming at higher levels of abstraction. Higher levels of abstraction are provided to free the programmer from the details of the embodiment, to reduce development time and to reduce the likelihood of errors. In some cases, it is impossible to determine a priori where a variable in a higher level program is located. This is particularly true with regard to the common use of xe2x80x9cpointersxe2x80x9d in higher level programming languages, such as the xe2x80x9cCxe2x80x9d programming language. A subroutine that is used to compute and return one or more results is usually called with pointer-arguments that point to the locations at which to place the computed results. Note that the pointer-argument may point to an internal or an external data memory location, or a location in the program memory, and the subroutine is compiled without knowledge of which memory space(s) may be used to store the results when this routine is actually called. Therefore, each pointer-argument must include an identification of the memory space to which it points, and the compiled code for the subroutine must include each of the forms of memory access (MOV, MOVX, MOVC instructions) for each possible memory space identification associated with each pointer. That is, although the intent of discrete memory space partitioning is to reduce the amount of memory required to effect memory accesses, the savings are often obviated by the generation of a substantial amount of code when the processor-level program instructions are generated from higher level programming instructions. This inefficiency may also occur when the processor-level program instructions are created directly for subroutines that are purposely designed to be usable regardless of the particular arguments provided.
It is an object of this invention to provide a processing system and method that allows for extended memory addressing while maintaining compatibility with legacy devices. It is a further object of this invention to provide a processing system and method that allows for the use of a common addressing scheme independent of the location or type of memory being addressed. It is a further object of this invention to provide a processing system and method that allows for the use of either a location-dependent or location-independent addressing scheme for memory access.
These objects and others are achieved by providing a processing system that supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a xe2x80x9cuniversalxe2x80x9d memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.